The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a contact area for connecting upper and lower conductive layers.
FIG. 1 shows a conventional semiconductor device having a contact area for connecting upper and lower conductive layers. This semiconductor device has semiconductor substrate 1, insulating layer 2 formed on substrate 1 and having a thickness of, e.g., 4,000.ANG. (=0.4 .mu.m), lower conductive layer 3 formed on insulating layer 2 and having a thickness of, e.g., 3,000 to 4,000.ANG., thick insulating layer 4 formed on layers 2 and 3 to expose part of layer 3 and having a thickness of, e.g., 7,000.ANG., and upper conductive layer 5 formed on layer 4 and the exposed portion of lower conductive layer 3. The contact portion of lower and upper conductive layers 3 and 5 constitutes contact area 6. Layers 2 and 4 are made of the same insulating material such as SiO.sub.2.
Conventionally, when part of layer 3 is exposed, i.e., when a contact hole is formed in layer 4, an anisotropic etching method, e.g., a reactive ion etching method (RIE), is used to partially etch layer 4, so that the integrated circuit can be micropatterned. Along with the micronization of the integrated circuit pattern, the width and thickness of layer 3 must be reduced. Furthermore, in a static RAM, a polycrystalline silicon layer for forming lower conductive layer 3 must be selectively made very thin in order to make the selected part highly resistive and form a high-resistance element of the polycrystalline silicon layer as the load element of each memory cell. In this manner, as the integrated circuit is micropatterned and highly integrated, the thickness of layer 3 tends to be further reduced. This is also applied to an active element formed in part of the polycrystalline silicon layer.
When a contact hole is formed in layer 4 by the RIE method, the ratio of the etching rate of layer 4 to the etching rate of layer 3 (etching selectivity) is not very large, but usually less than 10. Accordingly, when lower conductive layer 3A having a very small thickness of, e.g., 500.ANG., is formed, if part of insulating layer 4 is etched at a small etching selectivity and an etching time 1.5 times a normal etching time in consideration of an allowable error or processing margin, not only the part of layer 4 but also the corresponding portion of layer 3A is etched. In addition, part of insulating layer 2 is etched to partially expose substrate 1. In this state, when upper conductive layer 5A is formed, it is in direct contact with the exposed portion of substrate 1.